(1) Field of the Invention
The present invention relates to a semiconductor memory device comprising a dynamic random access memory (DRAM).
(2) Description of Related Art
In dynamic random access memories (hereinafter, referred to as DRAMs) having a relatively large storage capacity, there have been typically used so-called redundancy repair techniques in which when a defect occurs in a memory cell during their manufacturing process, the defect is repaired by replacing a defective cell with a previously prepared spare memory cell. In this way, defects due to the manufacturing process are repaired, leading to improved yields.
The redundancy repair techniques have various schemes. In particular, the following three schemes have conventionally been employed.
The first scheme is a line-based redundancy scheme in which lines such as spare rows (word lines) and columns (bit lines or data lines) are provided and a row or column line including a defective memory cell is replaced with a spare line;
the second scheme is a block redundancy scheme in which one or more spare memory cells are prepared for each unit of arbitrary number of memory blocks and a defective cell is replaced with a spare cell in the corresponding unit of memory blocks; and
the third scheme is a bit redundancy scheme in which a defective bit is replaced with a spare bit on a bit-by-bit basis.
Out of these schemes, the line-based repair scheme that is the first repair scheme is most superior and has been actually and widely used in view of the following: an increase in the circuit area caused by the placement of spare memory cells, the flexibility for repairs, repairs against a few bit defects, for example, taking place in a process step for forming a diffusion layer or a process step for forming a cell or against line defects, for example, taking place in a process step for forming a metal interconnect, and further the complexity of a control circuit itself for controlling redundancy repairs.
(First Known Example)
A row redundancy scheme that is a kind of line-based redundancy scheme will be described hereinafter as a first known example. The row redundancy scheme is a scheme for performing a redundancy repair by replacing a defective word line with a spare word line.
FIG. 5 shows the first known example, i.e., the block structure of a DRAM device employing a row redundancy scheme.
As shown in FIG. 5, the known DRAM device comprises a plurality of memory blocks 100 each consisting of a memory cell array 101, a redundancy word line 102 and a sense amplifier array 103, a read/write (R/W) amplifier 104 for reading/writing data from/to each memory cell array 101, a data input/output (I/O) buffer 105 for externally inputting/outputting data, and a comparator 107 for comparing an externally input address with a previously detected defective address.
The sense amplifier array 103 in each memory block 100 is electrically connected via a plurality of common data bus lines 106 to the read/write amplifier 104.
The comparator 107 receives an input address and a defective address. In the comparator 107, if the input address coincides with the defective address, the redundancy word line 102 in the particular memory block 100 is selected. If not, a word line belonging to the memory cell array 101 is selected.
Such an above technique in which one redundancy word line 102 is provided in each memory block 100 increases the number of redundancy word lines 102 with the increasing number of blocks. This increases the circuit area.
Furthermore, in order to achieve increase in processing speed and reduction in power, a method is effective in which the memory block 100 is divided into smaller units to reduce the number of memory cells per unit block. However, also in this case, the provision of a redundancy word line 102 in each memory block 100 increases the circuit area, thus leading to increased demerits.
An alternative method is to provide redundancy memory blocks, instead of the provision of a redundancy word line 102 in each memory block 100. In this case, however, the circuit area increases by the area of sense amplifiers because a sense amplifier is essential for DRAM cells.
(Second Known Example)
Next, a DRAM device employing a bit redundancy system is given as a second known example (see, for example, Japanese Unexamined Patent Publication No. 2002-298596). According to this publication, the regions of a sense amplifier array placed in each memory block and row and column decoders are partly employed as SRAM redundancy cells, and defective cells are replaced on a cell-by-cell basis.
In the redundancy repair technique for a DRAM device according to the first known example, the provision of a redundancy word line 102 in each memory block 100 significantly increases the circuit area, resulting in reduced repair efficiency.
The redundancy repair technique for a DRAM device according to the second known example is a bit redundancy scheme, and therefore cannot repair line defects. Furthermore, in this scheme, it becomes more difficult to reserve space to place SRAM cells in the regions shown in the above publication as the process geometry becomes finer. In addition, when the processes have matured, the method of placing redundancy SRAM cells in each memory block must provide low repair efficiency.